1. Field of the Invention
This invention relates to electronic design automation tools and, more particularly, to minimum timing violations and path delay analysis.
2. Description of the Related Art
During the design of an integrated circuit (IC), an automated design tool may be used to create the IC. The design flow includes a number of steps including schematic capture, circuit simulation, netlist creation, circuit layout, and others. In addition, to identify potential timing problems in the circuit, timing analysis is performed on the netlist. More particularly, the time that it takes signals such as clocks and data to propagate along a given path from a source to a destination is referred to as the path delay. There are a variety of ways of performing timing analysis. For example, static timing analysis and statistical timing analysis are both commonly used.
The result of the timing analysis may be a path report that lists all paths that violate the minimum timing rules for the design. The path report may list the paths and their respective delays. These paths may be referred to as minimum timing violation (mintime violation) paths. Generally, a mintime violation results when either the datapath is too fast or the clock or timing path is too slow such the data is changing or is gone before the data can be captured. In conventional design tools, to fix the minimum timing violations, the designer may iteratively make manual fixes (or changes to the netlist) by adding delays, and each time rerunning the timing analysis tool to verify the fixes, which may take many hours to run, and which may introduce maximum timing violations.